1. Field of the Invention
The invention relates in general to a method of forming semiconductor integrated circuits (ICs), and more particularly to a method of aligning of an aligner used during an isolation process.
2. Description of the Related Art
Sallow trench isolation (STI) structures are now widely used for IC devices isolation. Typically silicon nitride is used as a hard mask to etch a semiconductor substrate anisotropically to form a substantially vertical trench. The trench is filled with oxide to be a device isolation structure. The upper surface of the isolation structure is about at the same level as the top surface of the semiconductor substrate. The thickness of the STI structure provides effective isolation and is suitable for smaller size devices.
FIGS. 1A-1F are cross-sectional views showing steps of a conventional process of forming a shallow trench isolation structure. As shown in FIG. 1A, a semiconductor substrate 100 with an aligning mark 102 formed therein is provided. The aligning mark called "zero mark" is used for alignment and has a concave profile. A pad oxide layer 104 and a silicon nitride layer 106 are subsequently formed on the substrate 100.
In FIG. 1B, a defined photoresist layer 108 is provided over the silicon nitride layer 106. The silicon nitride layer 106 and the substrate 100 are partially removed with the defined photoresist layer 108 to form a trench 110 in the substrate 100.
In FIG. 1C, a side-wall oxide layer 111 is formed on the trench 110 side-wall after removing the defined photoresist layer 108. An oxide layer 112 with a thickness of about 7000 .ANG. is formed by low pressure chemical vapor deposition (LPCVD) and densified at a temperature of 1000.degree. C.
In FIG. 1D, a portion of the oxide layer 112 is removed by chemical mechanical polishing (CMP), using the silicon nitride layer 106 as a polishing stop layer so that the oxide layer 112a is left in the trench 110. In addition, some oxide 112b remained in the silicon nitride layer 106 in the aligning mark 102.
As shown in FIG. 1E, the CMP process provides an global planarized surface. Since the alignment for patterning a polysilicon layer on the structure shown in FIG. 1D is performed by optical theory of grating there must be a step-height profile at the aligning mark 102. The oxide 112b remained in the aligning mark 102 makes the underlying silicon nitride layer to be removed difficultly, so that in the conventional method for forming a STI structure the oxide 112b within the aligning mark 102 has to be cleared out. A photoresist layer 114 is provided over the structure shown in FIG. 1D with an opening aligned over the aligning mark 102. The oxide 112b remained in the aligning mark 102 and the exposed silicon nitride layer 106 are removed. Then, plasma is used to perform a cleaning step.
In FIG. 1F, the remained silicon nitride layer 106 and the pad oxide layer 104 are removed after removing the photoresist layer 114. A gate oxide layer 116 is formed on the structure surface after cleaning. Then, a polysilicon layer 118 with a step-height profile over the aligning, mark 102 is formed on the gate oxide layer 116.
The conventional process must use a clear-out process to remove silicon nitride on the aligning mark to make the polysilicon layer which is formed at the subsequent step having the step-height profile. The clear-out process requires the formation of a photoresist layer and many other steps. It does not only increase the consumption of materials (such as photoresist, etchant, etc.), and thus increases the fabrication cost, but also occupy a machine with a long operation time.